Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several\ntechnological and scientific areas such as synthetic aperture radar, computational photography,\nmedical imaging, telecommunications, seismic analysis and so on. However, its computation\ncomplexity is high. In this paper, we describe an efficient NFFT implementation with a hardware\ncoprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that\nemploys an Advanced RISC Machine (ARM) as Processing System with Programmable Logic\nfor high-performance digital signal processing through parallelism and pipeline techniques.\nThe algorithm has been coded in C language with pragma directives to optimize the architecture of\nthe system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool\nthat simplifies the interface and partitioning between hardware and software. This provides shorter\ndevelopment cycles and iterative improvements by exploring several architectures of the global\nsystem. The computational results shows that hardware acceleration significantly outperformed the\nsoftware based implementation.
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